1. Field of the Invention
The invention relates to a circuit arrangement for monitoring a binary signal which in normal operation exhibits at least one level shift within a characteristic waiting time and which has two flip-flops that receive control pulses from a control unit, the interval between control pulses being at least as long as the characteristic waiting time.
2. Description of the Related Art
A circuit arrangement with the features mentioned is known from European Patent EP No. 0 191 421. In that known arrangement, the control unit is a frequency divider which divides the bit clock pulse of the binary signal to be monitored and connects its output to the reset input of a first D flip-flop. The division ratio of the divider is selected so that the interval between two reset pulses for the first D flip-flop matches that of the abovementioned characteristic waiting time. The signal to be monitored is fed to the clock input of the first D flip-flop. With a second D flip-flop, which is clocked with the output signal of the divider, i.e. with the reset pulses for the first D flip-flop, the state of the first D flip-flop is queried and accepted by the second D flip-flop. It can then be seen from the state of the second D flip-flop whether an edge shift occurred or not during the characteristic waiting time. If no edge shift occurred, this is taken as a criterion indicating the presence of a defect.
The known arrangement can be integrated; however an arrangement of this kind is seldom used on its own as an integrated component, rather it is usually only a small part of the functional units integrated on a chip.
With chips with a high integration density, it is very important to have simple, yet reliable test methods with which the proper functioning of all the units integrated on a chip can be checked. A prerequisite for a method of this kind, which we will not discuss in more detail here, is, for example, to clock all flip-flops with the same clock pulse. In the known circuit arrangement, the first flip-flop is clocked by edges of the binary signal to be monitored and the second by edges of the clock pulses. Therefore a chip having the known arrangement as a component part would have to be tested using a special procedure.